Prince Kumar Singh, Kamalaksha Baral, Sanjay Kumar, Sweta Chander, and Satyabrata
Jit, “Analytical drain current model of stacked oxide SiO 2 /HfO 2 cylindrical gate tunnel
FETs with oxide interface charge,” Indian J Phys , June 2019 .(Accepted). (Impact Factor: 1.947).
Prince Kumar Singh, Kamalaksha Baral, Sanjay Kumar, Sweta Chander, Manas Ranjan
Tripathy, Ashish Kumar Singh, and Satyabrata Jit, “Source pocket engineered underlap
stacked-oxide cylindrical gate tunnel FETs with improved performance: design and
analysis,” Applied Physics A, Feb.2020 .(Accepted).(Impact Factor: 2.584).
Prince Kumar Singh, Kamalaksha Baral, Sanjay Kumar, Manas Ranjan Tripathy,
Ashish Kumar Singh, Rishibrind Kumar Upadhyay and Satyabrata Jit, “Analytical Drain
Current Model for Source Pocket Engineered Stacked Oxide SiO
2
/HfO
2
Cylindrical Gate
TFETs,” Silicon, May 2020.(Accepted).(Impact Factor: 2.670).
Sanjay Kumar, Ekta Goel, Kunal Singh, Balraj Singh, Prince Kumar Singh,
Kamalaksha Baral and Satyabrata Jit, “2-D Analytical Modeling of the Electrical
Characteristics of Dual-Material DG TFETs with a SiO2/High-k Stacked Gate-Oxide
Structure,” IEEE Transactions on Electron Devices, Mar. 2017.(Accepted).Impact
Factor: 2.917.
Sanjay Kumar, Kunal Singh, Sweta Chander, Ekta Goel, Balraj Singh, Prince Kumar
Singh, Kamalaksha Baral and Satyabrata Jit, “2-D Analytical Drain Current Model of
Heterojunction DG TFETs with a SiO2/High-k Stacked Gate-Oxide Structure,” IEEE
Transactions on Electron Devices, Nov. 2017.(Accepted).Impact Factor: 2.917.
Kamalaksha Baral, Prince Kumar Singh, Sanjay Kumar, Sweta Chander, and Satyabrata
Jit, “Ultrathin Body Nanowire Hetero-dielectric Stacked Asymmetric Halo Doped
Junction less Accumulation Mode MOSFET for Enhanced Electrical Characteristics and
Negative Bias Stability,” Superlattices and Microstructures,
Dec.2019.(Accepted).(Impact Factor: 2.658).
Kamalaksha Baral, Prince Kumar Singh, Sanjay Kumar, Ashish Singh, Manas Tripathy,
Sweta Chander, and Satyabrata Jit, “2-D analytical modeling of drain and gate-leackage
current of cylindrical gate asymmetric halo doped dual material-junction less
accumulation mode MOSFET,” International Journal of Electronics and
Communications, Jan.2020.(Accepted).(Impact Factor: 3.183).
Kamalaksha Baral, Prince Kumar Singh, Sanjay Kumar, Ashish Singh, Manas Tripathy,
Sweta Chander, and Satyabrata Jit, “A 2-D compact DC model for engineered nanowire
JAM-MOSFETs valid for all operating regimes,” Semiconductor Science and
Technology, May 2020.(Accepted).(Impact Factor :2.361).
Sanjay Kumar, Kunal Singh, Kamalaksha Baral, Prince Kumar Singh, and Satyabrata
Jit, “2-D Analytical Model for Electrical Characteristics of Dual Metal Heterogeneous
Gate Dielectric Double-Gate TFETs with Localized Interface Charges,” Silicon, July
2020. (Accepted). (Impact Factor: 2.670).
Kamalaksha Baral, Prince Kumar Singh, Gautam Kumar, Ashish Kumar Singh, Manas
Ranjan Tripathy, Sanjay Kumar, Satyabrata Jit, “Impact of ion implantation on stacked
oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and
circuit level analysis,” Materials Science in Semiconductor Processing,
2021(Accepted).(Impact Factor:3.927).
Kamalaksha Baral , Prince Kumar Singh, Sanjay Kumar, Ashish Kumar Singh,
Deepak Kumar Jarwal , Satyabrata Jit, “A unified 2-D model for nanowire junctionless
accumulation and inversion mode MOSFET in quasi-ballistic regime” Solid-State
Electronics, 2022.(Accepted).(Impact factor:1.901).
Prince Kumar Singh, Sanjay Kumar, Sweta Chander, Kamalaksha Baral, and Satyabrata
Jit ,“ Impact of Strain on Electrical Characteristic of Double-Gate TFETs with a
SiO2/HfO2 Stacked Gate-Oxide Structure,” 14th IEEE India Council International
Conference (INDICON-2017) , IIT Roorkee, Roorkee , India, Dec.15-17, 2017.
Prince Kumar Singh, Kamalaksha Baral, Sweta Chander, Sanjay Kumar, Manas Ranjan
Tripathy, Ashish Kumar Singh, and Satyabrata Jit, “Impact of Gate Dielectrics on
Analog/RF Performance of Double Gate Tunnel Field Effect Transistor, ” 3rd
International Conference on Electronics, Materials Engineering & Nano-Technology
(IEMENTech-2019) , IEM Kolkata , India, Aug.29-31, 2019 .
Prince Kumar Singh, Kamalaksha Baral, Sanjay Kumar, Ashish Kumar Singh, Manas
Ranjan Tripathy, Rishibrinda Kumar Upadhyay and Satyabrata Jit, “Subthreshold Swing
Modeling of Gaussian Doped Double-Gate MOSFETs and its Validation Based on
TCAD Simulation,” 6
th
IEEE International Conference on Electronics, Computing and
Communication Technologies (CONECCT-2020), IEEE Bangalore Section, Bangalore,
India, Jul.2-4, 2020.
Prince Kumar Singh, Kamalaksha Baral, Ashish Kumar Singh, Manas Ranjan Tripathy,
Rishibrind Kumar Upadhyay, Abhinav Pratap Singh, Satyabrata Jit, “Influence of
Temperature on Analog/Radio Frequency Appearances of Heterojunction Cylindrical
Gate Tunnel FETs,” IEEE International Conference on Computing Power and
Communication Technologies (GUCON-2020), Radisson Blu Greater Noida, India,Oct.2-
4,2020.
Prince Kumar Singh, Kamalaksha Baral, Sanjay Kumar, Manas Ranjan Tripathy,
Ashish Kumar Singh, Rishibrinda Kumar Upadhyay, and S. Jit, “Impact of Temperature
on DC and AC Characteristics of Stacked Oxide SiO2/HfO2 Cylindrical Gate Tunnel
FETs” 2020 5th IEEE International Conference on Emerging Electronics (ICEE- 2020),
pp. 1-4.
"Recent Advances and Challenges in Nano-electronics Devices (RACND-2021)" from
13/12/2021 to 17/12/2021 at IIIT Bhagalpur.
Next-Generation Nano-electronics Devices, Circuits and its Applications using EDA
tools” (24 -28 February, 2021)
Five-Day FDP – cum - STTP on Simulation, Modelling and Application of Advanced
Semiconductor Devices m 05 - 09 July, 2021, organized by the Department of
Electronics Engineering, Harcourt Butler Technical University, Kanpur, Uttar Pradesh,
India - 208002.
INUP Familiarization workshop on nanofabrication technologies organized by IIT
Bombay, May 25-27, 2017.
Vesvesvaraya Fellowship awarded by Ministry of Electronics & Information Technology
(MeitY) Government of India for the 5year (July ’15 - July ’20) to pursuing Ph.D.
Best paper award for the paper titled , “ Device and Circuit Level Performance
Comparison of Vertically Grown All-Si TFET and Ge/Si Hetero-Junction TFET” in
the category VLSI at "6th International Conference on Electronics, Computing and
Communication Technologies" , IEEE CONECCT 2020 organized by IEEE Bangalore
Section from 2-4 July, 2020
